In memory systems having multiple memory ranks operating in independent time domains and coupled to a shared command path, delay is generally imposed between commands transmitted to different memory ranks to accommodate time-domain switching. While memory systems have historically enjoyed surplus command bandwidth that could be devoted to time domain switching (i.e., rendering the switching transparent), demand for reduced transaction granularity in modern systems is consuming the surplus, driving up command path utilization to the point where insufficient time remains to accommodate time-domain switching. As a result, memory controllers that employ micro-threading, module-threading or otherwise require high command signaling bandwidth are increasingly forced to insert delays or “bubbles” between commands directed to different memory ranks, thus incurring timing penalties that increase memory latency and reduce data throughput. In some cases, designers are limiting memory systems to a single rank to avoid such rank-switch timing penalties, sacrificing memory capacity to avoid compromised performance.